DAQ VXI-SC-1102 Manual de Instruções descarregar pdf (Página 53)

Chapter 7 PC-TIO-10 Timing I/O Device

DAQ Hardware Overview Guide 7-4 www.ni.com

Figure 7-2. Am9513 Counter Timing and Output Types

Figure 7-2 represents a counter generating a delayed pulse and

demonstrates the four forms the output pulse can take given the four

different types of output signals supported. The TC toggled positive logic

output looks like what would be expected when generating a pulse. For

most of the Counter/Timer functions, TC toggled output is the preferred

output configuration; however, the other signal types are also available. The

starting signal shown in Figure 7-2 represents either a software starting of

the counter, for the No-Gating mode, or some sort of signal at the GATE

input. The signal could be either a rising edge gate or a high-level gate. If

the signal is a low-level or falling edge gate, the starting signal simply

appears inverted. In Figure 7-2, the counter is configured to count the rising

edges of the timebase; therefore, the starting signal takes effect on the rising

edge of the timebase, and the signal output changes state with respect to the

rising edge of the timebase.

0 < sync period < 1

Timebase

Starting

Signal

TC Toggle

Output

TC Pulse

Output

units = timebase period

Positive

Negative

Positive

Negative

1 1

1 2 ... 48 49 50 51 52 53 54 55 56 57 58 ... 150 151

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DAQ VXI-SC-1102 Manual de Instruções Página 53