DAQ VXI-SC-1102 Manual de Instruções Página 52

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Chapter 7 PC-TIO-10 Timing I/O Device
©
National Instruments Corporation 7-3 DAQ Hardware Overview Guide
High-Level Gate N–1 Gating—the counter is active when the gate
input of the next lower-order counter is at high-logic state. Otherwise,
the counter is suspended.
Counter operation starts and stops relative to the selected timebase. When
you configure a counter for no gating, the counter starts at the first
timebase/source edge (rising or falling, depending on the selection) after
the software configures the counter. When you configure a counter for
gating modes, gate signals take effect at the next timebase/source edge. For
example, if you configure a counter to count rising edges and to use the
falling edge gating mode, the counter starts counting on the next rising edge
after it receives a high-to-low edge on its GATE input. Thus, some time is
spent synchronizing the GATE input with the timebase/source. This
synchronization time creates a time lapse uncertainty from zero to one
timebase period between the application of the signal at the GATE input
and the start of the counter operation.
The counter generates timing signals at its OUT output. If the counter is not
operating, you can set its output to one of three states—high-impedance
state, low-logic state, or high-logic state.
The counters generate two types of output signals during counter operation:
TC pulse output and TC toggled output. A counter reaches TC when it
counts up (to 65,535) or down (to 0) and rolls over. In many counter
applications, the counter reloads from an internal register when it reaches
TC. In TC pulse output mode, the counter generates a pulse during the cycle
in which it reaches TC. In TC toggled output mode, the counter output
changes state on the next source edge after reaching TC. In addition, you
can configure the counters for positive logic output or negative (inverted)
logic output. Figure 7-2 shows examples of the four types of output signals
generated.
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